1. Field of the Invention
The present invention relates to an A/D conversion apparatus and, particularly, to an A/D conversion apparatus that splits data into high-order bits and low-order bits for conversion.
2. Description of the Related Art
An analog-to-digital (A/D) conversion apparatus samples an analog input signal at a sample/hold circuit and converts the sampled analog input signal to a digital signal at an A/D converter circuit. There are two types of A/D conversion apparatus: successive approximation type and flash type. FIG. 8 is a block diagram that schematically shows a flash A/D conversion apparatus. The flash A/D conversion apparatus includes a voltage dividing resistor array 80, a plurality of comparators 81, and an encoder 82. The output of the encoder 82 is connected to a digital output terminal 83. The input of the encoder 82 is connected to the plurality of comparators 81. One input of each comparator 81 is connected to an analog input terminal 84 and the other input of each comparator 81 is connected to one end of each voltage dividing resistor R. One end of the voltage dividing resistor array 80 as a whole is connected to a reference input voltage terminal 85 and the other end is grounded.
The operation of the flash A/D conversion apparatus is described herein. An analog input voltage Ain from the analog input terminal is supplied to each comparator at a time. The analog input voltage Ain is compared with a reference input voltage that is supplied from the reference input voltage terminal 85 and divided by each voltage dividing resistor R. The encoder 82 encodes an analog input voltage into binary bit-string data based on the output from the comparator 81.
Thus, analog to digital conversion involves voltage comparison at each comparator and encoding to bit-string data at the encoder. Each bit of the bit string is weighted according to a reference voltage.
A conventional A/D conversion apparatus having A/D converters in multiple stages is disclosed in Japanese Unexamined Patent Application Publication No. 5-63571. A conventional A/D conversion apparatus that generates a 8-bit digital signal includes flash A/D converters in two stages so as to use a smaller number of comparators. FIG. 9 shows the A/D conversion apparatus.
In the A/D conversion apparatus shown in FIG. 9, a high-order A/D conversion apparatus 91 converts high-order 5 bits. A low-order A/D conversion apparatus 92 receives a reference voltage based on a conversion result of the high-order 5 bits. After that, the low-order A/D converter 92 converts low-order 3 bits. The output of the high-order A/D conversion apparatus 91 and the output of the low-order A/D conversion apparatus 92 are coupled at a coupler and output as 8-bit digital data Dout.
However, even with the two-stage configuration for high-order bits and low-order bits, the flash A/D conversion apparatus still requires a large number of comparators. Use of a large number of comparators causes large power consumption in the A/D conversion apparatus and large circuit scale.
On the other hand, use of a successive approximation A/D conversion apparatus requires a smaller number of comparators; however, it requires a comparator capable of converting a voltage of ¼ to ⅛ of a voltage per 1LSB (LSB voltage) that is obtained by dividing a full scale input voltage by 2n (n is resolving power). To compare extremely small voltages, the successive approximation A/D conversion apparatus requires a comparator of multistage configuration, which results in large power consumption.
As described above, the present invention has recognized that conventional A/D conversion apparatus require a large amount of power due to a large number of comparators and a high level of accuracy required for comparators, thus incapable of achieving low power consumption.